1. Field of the Invention
The present invention relates to a sync signal processing device for a combined video appliance. In particular, the present invention relates toga sync signal processing device for a television (TV) receiver combined with a personal computer (PC) which can directly process a PC sync signal through a sync signal processing circuit of the TV receiver to achieve horizontal and vertical driving and deflection.
2. Description of the Prior Art
Recently, as a TV receiver combined with a PC is being introduced, techniques for displaying a PC signal on a screen of a TV receiver by processing the PC signal through internal circuits of the TV receiver have been developed.
A conventional sync signal processing device of a TV receiver is illustrated in FIG. 1. Referring to FIG. 1, the conventional device includes a video processing section 1 for processing a received TV video signal and separating horizontal and vertical sync signal from the video signal, a sync signal processing circuit 2 for producing horizontal and vertical driving signals in accordance with the horizontal and vertical sync signals separated through the video processing section 1, a horizontal output circuit 3 for performing a horizontal deflection in accordance with the horizontal driving signal outputted from the sync signal processing circuit 2, a vertical output circuit 4 for performing a vertical deflection in accordance with the vertical driving signal outputted from the sync signal processing circuit 2, and a microcomputer 5 for controlling the operation of the sync signal processing circuit 2.
According to the conventional sync signal processing device of the TV receiver as constructed above, the TV video signal processed by the video processing section I is inputted to the sync signal processing circuit 2. In the sync signal processing circuit 2, the horizontal and vertical sync signals are separated from the TV video signal, and the horizontal and vertical driving signals HD and VD are produced in accordance with the separated horizontal and vertical sync signals to be inputted to the horizontal and vertical output circuits, respectively.
At this time, the microcomputer 5 varies correction data of the sync signal processing circuit 2 to control the correction of the picture displayed on the screen, and the horizontal and vertical output circuits 3 and 4 perform the horizontal and vertical outputs (deflections) in accordance with the input horizontal and vertical driving signals, respectively.
The sync signal process performed by the sync signal processing circuit 2 will now be explained in detail.
The sync signal processing circuit 2 is provided with a horizontal sync separating section 6 for separating the horizontal sync signal Hsync inputted from the video processing section 1, a horizontal locking section 7 for locking the horizontal sync signal outputted from the horizontal sync separating section 5 into a horizontal blanking section 8 for processing a horizontal blanking in compliance with a, input horizontal deflection pulse signal, a phase detecting section 9 for detecting the phase of the horizontal sync signal provided from the horizontal sync separating section 6, an oscillation section 10 for oscillating with a frequency of 503.5 KHz in accordance with the output of the phase detecting section 9, a divider 11 for dividing by 32 the output of the oscillation section 10 and providing the divided frequency to the phase detecting section 9 to achieve a phase locked loop (PLL), a phase detecting section 12 for detecting the phase of the output of the divider 11 and the output of the horizontal blanking section 9, a phase shifting section 13 for shifting the output of the phase detecting section 12, a horizontal driving section 14 for providing to the horizontal output circuit 3 the horizontal driving signal HD in accordance with the output of the phase shifting section 13, a phase detecting section 15 for detecting the phase of the output of the divider 11, an oscillation section 16 for oscillating with a frequency of 16 MHz in accordance with the output of the phase detecting section 15, and a divider 17 for dividing by 1024 the output of the oscillation section 16 and providing the divided frequency to the phase detecting section 15 to achieve a PLL.
The sync signal processing circuit 2 is also provided with a vertical sync separating section 18 for separating the vertical sync signal vsync inputted from the video processing section 1, a count-down processor 19 for performing a down-counting with respect to the vertical sync signal separated by the vertical sync separating section 18 and the output signal of the divider 17, a digital signal processor 20 for processing a digital signal for correcting the deflection in response to the output of the count-down processor 19, a vertical driving section 21 for providing the vertical driving signal VD to the vertical output circuit 4 by performing a digital-to-analog conversion of a vertical sawtooth wave, low-pass-filtering, and amplification in response to the data outputted from the digital signal processor 20, a horizontal digital-to-analog (D/A) converter 22 for converting the horizontal data outputted from the digital signal processor 20 into an analog signal, an automatic frequency control (AFC) compensation section 23 for compensating for the output of the horizontal D/A converter 22 to provide the compensated signal to the phase shifting section 13, and a bus decoder 24 for performing an I.sup.2 C bus decoding between the processor 19 and the microcomputer 5.
The operation of the conventional sync signal processing device as constructed above will be explained.
The horizontal sync separating section 6 separates the horizontal sync signal form the input video signal, and the horizontal locking section 7 is locked into the horizontal deflection pulse signal inputted to the horizontal blanking section 8. The horizontal blanking section 8 performs the horizontal blanking process of the inputted horizontal deflection pulse signal and provides the processed signal to the horizontal locking section 7, phase detecting section 12, and the count-down processor 19.
The phase detecting section 9 detects the phase of the horizontal sync signal separated by the horizontal sync separating section 6 and the signal obtained by dividing by 32 the oscillated signal 32 f.sub.H VCO of 503.5 KHz outputted from the oscillation section 10, and controls the operation of the oscillation section 10 in accordance with the detected phase, so that an AFC loop is effected to make the oscillation section 10 produce a horizontal pulse signal synchronized with the horizontal sync signal.
The horizontal pulse signal, which is divided through the divider 11, is inputted to the phase detecting section 12. The phase of the horizontal pulse signal is compared with that of the output of the horizontal blanking section 8, and the result of the phase comparison is inputted to the phase shifting section 13 to control the phase of the horizontal driving output pulse signal. The horizontal driving section 14 outputs the horizontal driving pulse signal HD to the horizontal output circuit 3 in response to the output of the phase shifting section 13.
The horizontal pulse signal divided through the divider 11 is also inputted to the phase detecting section 15, and the phase detecting section 15 compares the phase of the output of the divider 11 with that of the signal obtained by dividing by 1024 the clock signal of 16 MHz produced from the oscillation section 16, so that the operation of the oscillation section 16 is controlled in accordance with the comparison result.
Meanwhile, the vertical sync separating section 18 separates the vertical sync signal from the input video signal and provides the separated vertical sync signal to the count-down processor 19. The count-down processor 19 counts down the vertical sync signal and the clock signal divided by and inputted from the divider 17, and provides the counted data to the digital signal processor 20 for correcting the deflection.
The digital signal processor 20 receives the counted data from the count-down processor 19 and the clock signal form the divider 17, and produces the digital data of the vertical sawtooth wave, parabolic wave, and AFC compensation including the compensation for the picture distortion. The vertical driving section 21 performs the D/A conversion of the vertical sawtooth wave, low-pass-filtering, amplification, etc., and provides the vertical driving pulse signal VD produced by the above-described signal process to the vertical output circuit 4 to effect the vertical deflection.
The horizontal D/A converter 22 converts the AFC compensation data into the analog signal and provides the analog signal to the AFC compensation section 23, so that the AFC compensation section 23 superimposes the compensation signal on the output of the phase shifting section 13 to achieve the compensation for the picture distortion.
The microcomputer 5 controls the picture correction by decoding all the compensation data SCL and SDA through the bus decoder 24.
However, the conventional sync signal processing device of the TV receiver has the drawback that it cannot process the PC signal due to the frequency difference between the PC signal and the TV signal if the PC signal is processed as it is, not being frequency-converted. Further, the picture and the on-screen display (OSD) on the screen tremble in a vertical direction since the horizontal sync signal of the PC signal is not 15.75 KHz suitable for the IV signal during the vertical oscillation process even though the PC signal is processed through separate switching sections.